In electrical circuit technologies, many electrical circuit devices or apparatuses, such as printed circuit boards (PCBs) or integrated circuits (ICs), include vias and traces that electrically connect component parts of or connections to and/or within the electrical device. However, as both speeds and circuit board layer counts increase, the transmission line effects of through-hole vias become increasingly important. Impedance and propagation delay are two transmission line effects, and the impedance can significantly impact signal integrity. In a lengthwise conductor of the via type, impedance is the square root of the ratio of inductance per unit length to capacitance per unit length. Also, vias tend to have very large capacitances due to the effects of pads and nearby reference planes. These physical issues may cause the impedance of a via to be much lower than the impedance of the traces on different layers connected by the vias. Such mismatched impedance(s) may lead to signal reflections, which can cause errors and an inability to reach theoretically maximal signal speeds. Signal propagation can be undesirably delayed by the comparative high capacitance of such vias.
Some attempts have been made to decrease such effects by focusing on decreasing the capacitance of the vias. Two such methods have included either removing some of the pads or creating large areas where the nearby reference planes have been removed, known as antipads. Removing unused pads is generally helpful, although pads do provide a mechanical stabilizing effect for the via; and yet, pads are still required on those layers where traces connect. Moreover, large antipads cause difficulty by reducing routing density since it is advisable to route nearby signals over solid sections of the reference planes.